Field-programmable gate arrays ("FPGAs") are known to those skilled in the art to include arrays of uncommitted, programmable logic cells having both combinational and sequential logic circuits therein. The logic cells are conventionally programmably interconnected with a programmable interconnect network. A complex user-defined logic function can thus be performed by an FPGA by appropriately programming and interconnecting the logic cells. It is desirous to provide a test strategy for the programmable resources provided in an FPGA.
Test strategies and systems are known in the art. Boundary scan techniques involve the provision of dual latch sets at the perimeter of a chip, in association with the I/O terminals. The latches are connected into a shift register. Test stimuli are loaded into a first latch of each set, applied to the internal circuit, and the second latch of each set is used to receive the response of the circuit to the test stimuli. These results can then be shifted out of the shift register and compared to expected results. Scan-in, scan-out, and several clock terminals are provided, and faults can be detected in the circuit without requiring an external test circuit at each I/O terminal. However, with increasing circuit densities, and especially considering the heterogeneous nature of the circuits in an FPGA, fault detection may be possible with boundary scan techniques, but fault isolation may be difficult. It is thus desirous to employ test systems which provide a larger degree of fault isolation, especially considering the density and heterogeneous nature of the resources and subsystems in an FPGA.
Level-sensitive scan design ("LSSD") test techniques are also known and involve segmenting a logic circuit into combinational and sequential logic circuitry. The sequential circuits are connected into a shift register which bound or segment regions of the combinational circuitry. Like boundary scan techniques, test stimuli are shifted into the resultant shift registers, applied to the combinational regions, and results are collected into the shift registers and shifted out for analysis. Again, reduced pin count testing is achieved because external test equipment need only access the scan-in, scan-out and appropriate clock pins.
The shift registers, or scan chains, require multiple scan clocks to operate. In addition, the shift registers, if used during operation and test, require clocks during both operation and test. Often, a user supplies clocks from a single clock source when operating the shift registers during test. In fact, a user may simultaneously test multiple integrated circuit devices at a card or board level, one or more of which may be an FPGA. When testing multiple integrated circuit devices, it is often desirable to employ a single test clock source and wiring. Having installed the wiring to support an operational clock source, it is desirous to use the same wiring to support a test clock signal source, so that wiring need not be supported for both operational and test clock signals.
Many FPGAs also include highly programmable operational clock distribution networks. One such network is disclosed in the above-incorporated sections of the U.S. patent application entitled "PROGRAMMABLE ARRAY CLOCK/RESET RESOURCE." The clock network disclosed therein accepts multiple clocks from off-chip sources. The network includes multiple levels of multiplexing for providing a high degree of operational clock selectivity in the array. However, LSSD scan clock multiplexing is not currently supported by this network. If storage circuits supported by such a network are also to be used for scan testing, it is necessary to integrate into the array a scan clock distribution strategy. In addition, it would be desirable to provide additional user options regarding the source from which to derive operational clocks, e.g., from the existing clock distribution network or a scan clock distribution network.
In summary, high-density FPGAs require test strategies having high degrees of fault isolation. If a scan chain is to be employed for testing, scan clock distribution strategies are required. These strategies should support, in one aspect, a single set of wiring for both operation and test. In addition, if a programmable clock network already exists in the array, the strategies should provide additional flexibility regarding the sources of the clocks used during operation and test.